The present invention relates to integrated circuits, and more particularly to a novel clocking scheme for FIFO (“first in-first out”) registers resident on an integrated circuit memory or the like.
It should be noted that a glossary of timing signal definitions can be found below in the Detailed Description of the invention.
Typically, the FIFO loading clock (FICLK) is a derivative of the main chip clock (INT CLOCK), i.e. frequency(FICLK)=frequency(INT CLOCK). The actual phase and/or enable time may have been shifted to provide the widest possible window, but the frequency of the FIFO loading clock was limited to that of the main chip clock.
The two main deficiencies of linking the FIFO loading clock to the main chip clock are either that the FIFO input clock window is too narrow to provide for adequate data capture in all cases, or the window is too wide and “data run-through” is allowed to occur.
In typical designs, the phase of the FICLK is allowed to vary and can be equal to the phase of either the internal JCLK or YCLK, or another phase, but the phase is ultimately derived from the internal clock. The reason this was typically done is because the internal YCLK is a free-running clock and fires every cycle, regardless of whether a read or write operation is in progress.
An example of a prior art FICLK clock scheme is shown in FIG. 1. The internal JCLK and YCLK clock signals are shown, followed by a read signal. FICLK-Y shows a YCLK-based FIFO loading clock and FICLK-J shows a JCLK-based FIFO loading clock. Other clocks in the data path are needed so that data from “READ-B” is not loaded with the “FICLK-A” pulse.
However, according to the JEDEC DDR2 standard, YCLK cannot free run, since its frequency can be one-half of the external clock, and can be started on any random JCLK cycle.
Two distinct problems arise due to the DDR2 standard.
Firstly, if the FICLK runs off of a derivate of the internal clock (JCLK), controlling the placement of the clock to accommodate the datapath/CAS latency relationship is easy, but the FICLK can become too narrow to provide an adequate data capture window. In the example shown in FIG. 2, the FICLK can be placed in various places with respect to JCLK and YCLK, but its frequency must match that of the internal clock, and therefore its actual “on” time must be less than that of the internal clock. I-data is the data that must be captured by the FICLK. In the example of FIG. 2, “FICLK-A” misses “I-data-A”. There is a delay 20 between the falling edge of the YCLK and the leading edge of the I-data due to simple R/C delays and device delays within the chip. This delay is significant because it changes with respect to temperature and supply voltages, while the period of the clock is fixed by the user. This means that the percentage of the clock period that delay 20 takes can change drastically depending on operating frequency, so a wide FICLK is required to guarantee correct data capture.
Secondly, if the FICLK runs off the YCLK, it may not align properly with what is required for the CL (CAS Latency). This is shown in the timing diagram of FIG. 3. It is possible that the output clock fires and attempts to fetch data from the FIFO register before the data is even loaded into the FIFO register by the FICLK. This is shown at time 30 in FIG. 3.
The two preceding examples of failure modes are examples only, and many such variations of possible failure modes are possible when combined with changes in frequency, data path speed, and CAS latency.
What is desired, therefore, is a clocking scheme for a FIFO that provides the widest possible window for capturing data while preventing data run-through.